IEEE

A Space Mapping Augmented Compact Model for Uncertainty Quantification of GaN HEMT Devices and Circuits in the Presence of Trap Effects

Abstract: In this article, an artificial neural network (ANN) augmented compact model is developed for the fast uncertainty quantification (UQ) of GaN high electron mobility transistors (HEMTs). The ...

Most lab testing quietly inflates 2D transistor performance, research reveals

For nearly two decades, two-dimensional (2D) semiconductors have been studied as a complement or possible successor to silicon transistors, promising smaller, faster and more energy-efficient ...
Duke Pratt School of Engineering

Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

Duke engineers show how a common device architecture used to test 2D transistors overstates their performance prospects in real-world devices.
IEEE

Design-Technology Co-Optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design

Abstract: A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line ...