Design And Reuse

The AI computing power chip unicorn Yixing Intelligence has secured another 2 billion yuan in financing, accelerating the commercial implementation and ecosystem leadership of ...

Recently, EVAS Intelligence, a domestic unicorn enterprise focused on RISC-V cloud AI computing power chips, has completed a new round of financing. The total financing amount of this round is nearly ...
Design And Reuse

Cadence PCIe 6.0 Clears First-Pass Compliance Testing

Cadence Design Systems announced that its PHY and controller IP for the PCIe 6.0 specification, implemented on TSMC’s N3 process, achieved first-pass compliance at PCI-SIG’s compliance workshop in ...
Design And Reuse

Chiplets Are Sparking an IC Design Revolution

Chiplets offer a different path forward, breaking monolithic designs into modular building blocks that can be combined within a single package. These integrated devices have evolved from discrete ...
Design And Reuse

Inside TSMC’s Evolving Design Ecosystem: Shaping the Future of AI, with AI

In this conversation, Aveek Sarkar, director of the ecosystem and alliance management at TSMC, shares updates on the foundry’s Open Innovation Platform (OIP) Ecosystem, including TSMC’s vision for ...
Design And Reuse

aiMotive and Cadence Demonstrate Layer-by-Layer Workload Placement Across Independent AI Engines

BUDAPEST, Hungary – aiMotive today announced a joint technology demonstration of explicit, per-layer neural network workload placement across aiMotive’s aiWare5 automotive NPU ...
Design And Reuse

Samsung considers expanding 4nm capacity as HBM4 demand rises

That's working out nicely for Samsung Electronics, which remains one of the largest players in the industry. The company is now reportedly considering expanding its 4nm capacity to meet the increasing ...
Design And Reuse

Accelerating Physical AI Through Cadence Silicon Solutions and Arm Total Design

Physical AI is a systems challenge, requiring a complete foundation that connects AI models to trusted silicon and ultimately ...
Design And Reuse

Alchip collaborates with Synopsys to Address Scale Up and Out Bandwidth Constraints

Today at the TSMC 2026 North America Open Innovation Platform® (OIP) Ecosystem Forum, Alchip Technologies presented a technical paper with Synopsys on how AI data center ASICs can overcome ...
Design And Reuse

Automated, Faster Specification to Sign-Off with IDS-AI

The other big news at DAC was the introduction of IDS-AI ™, our new agentic AI framework that automates your chip development ...
Design And Reuse

Dnotitia Brings Dedicated Vector Silicon to Server Scale at AI Infra Summit 2026

VDPU integrates with Dnotitia's Seahorse vector database and widely used vector-search software including Milvus, FAISS and ...
Design And Reuse

Overcoming power management IP challenges

To squeeze every drop of energy efficiency out of a modern chip, designers split the die into dozens of independent power domains. On paper, combining Dynamic Voltage and Frequency Scaling (DVFS), ...
Design And Reuse

Sofics Extends Interface Voltage Options in TSMC FinFET and Nanosheet Technologies

Sofics has been a member of the TSMC Open Innovation Platform® (OIP) IP Alliance since 2010. Many fabless companies have successfully integrated Sofics IP into their designs on TSMC process nodes ...