Duke Pratt School of Engineering

Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

Duke engineers show how a common device architecture used to test 2D transistors overstates their performance prospects in real-world devices.
Electronic Design

Test Setup Checks Transistors’ hFEs When Tight Control Is Important

This file type includes high resolution graphics and schematics. The spread of h FE values in a batch of transistors may be wide enough to cause unreliable performance during mass production of a ...
Nanowerk

Common lab design inflates 2D transistor performance by up to six times

Lab architecture used to test 2D semiconductors artificially boosts performance metrics, making it harder to assess whether these materials can truly replace silicon.
Interesting Engineering on MSN

The uncomfortable truth behind the hype around 2D semiconductor performance

For almost two decades, scientists have been trying to move beyond silicon, the material ...
EDN

Test tube transistor devised via molecular lithography

SAN FRANCISCO &#151 Researchers from the Israel Institute of Technology have developed what the university claims is a “transistor in a test tube”, built via sequence-specific molecular lithography.
Electronic Design

This Crucial WBG Power Transistor Reliability Test is Often Missing

There is a great deal of activity in wide bandgap (WBG) power electronics lately, with Gallium Nitride (GaN) and Silicon Carbide (SiC) devices getting a lot of attention due to the technologies’ ...
EDN

Coating lets nanotube transistors self-assemble on chips

Portland, Ore. — Next-generation semiconductors aim to harness the ballistic electron transport capabilities of pure carbon nanotubes, but until now there has been no easy way to integrate the tubes ...